Definition
Translation Lookaside Buffer
A TLB is a high-speed cache within the MMU storing recently used page-to-frame mappings for near-instantaneous address translation.
Access
Hit
The MMU finds the mapping in the TLB and produces the physical address immediately.
Miss
The MMU walks the page table in main memory, which is much slower, and loads the new mapping into the TLB.
Context Switching
On a process switch, the TLB must be flushed unless Address Space Identifiers (ASIDs) are used.
Typical
The TLB is small (typically 16–512 entries), fully associative, and accessed in less than one clock cycle. Hitrates above 99% are typical, because consecutive memory accesses often refer to the same page. This means most loads and stores need only one memory access instead of two: the TLB supplies the translation without a page table lookup.