Definition
Translation Lookaside Buffer (TLB)
A translation lookaside buffer (TLB) is a high-speed hardware cache located within the CPU’s Memory Management Unit (MMU). it stores the most recently used mappings from a page table, allowing for near-instantaneous address translation.
Mechanism
When the CPU needs to translate a virtual address:
- TLB Hit: The MMU checks the TLB for the page-to-frame mapping. If found, the physical address is calculated immediately.
- TLB Miss: If the mapping is not in the TLB, the MMU must perform a “page walk” by accessing the page table in main memory (which is much slower). The new mapping is then loaded into the TLB for future use.
Management
- Context Switching: Since page mappings are specific to each process, the TLB must be flushed (cleared) during a process switch unless it supports Address Space Identifiers (ASIDs).
- Size: Typically very small (16 to 512 entries) due to the high cost and power consumption of ultra-fast associative memory.