Compressed Instruction (RISC-V)

risc-v

Definition

Compressed Instruction (RISC-V)

A compressed instruction is a 16-bit RISC-V instruction encoding.

It is part of the compressed extension and represents a common operation in a shorter form than the standard 32-bit instruction. Compressed mnemonics are commonly prefixed with c..

Purpose

Compressed instructions reduce code size. Only a subset of RISC-V operations has a compressed form.

Formats

Compressed instructions use a 16-bit encoding.

• Some formats use a 3-bit register code instead of a 5-bit register number. These select registers x8 to x15.
• Immediates are typically 6 to 11 bits wide.
• The opcode is 2 bits wide.

The prime on a register name means the compressed register subset x8 to x15.

Compressed instructions can be divided into the following formats:

• CR-type instruction
• CI-type instruction
• CS-type instruction
• CS’-type instruction
• CB-type instruction
• CB’-type instruction
• CJ-type instruction
• CSS-type instruction
• CIW-type instruction
• CL-type instruction

Examples

Loop over an array

Consider the following C code:

int i;
int scores[200];
 
for (i = 0; i < 200; i = i + 1)
    scores[i] = scores[i] + 10;

One possible RISC-V translation is:

# s0 = scores base address, s1 = i
c.li s1, 0
addi t2, zero, 200
 
for:
    bge s1, t2, done
    c.lw a3, 0(s0)
    c.addi a3, 10
    c.sw a3, 0(s0)
    c.addi s0, 4
    c.addi s1, 1
    c.j for
done:

Explanation

• c.li, c.addi, c.lw, c.sw, and c.j have compressed forms.
• c.bge does not exist, so the loop test uses bge.
• addi t2, zero, 200 stays uncompressed because 200 is too large for the compressed immediate.