Lukas' Notes

RISC-V

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computer-architecture risc-v

Definition

RISC-V

RISC-V is an open standard instruction set architecture for computer systems.

Byte-Addressability

RISC-V uses byte-addressable memory, meaning each individual byte in memory has a unique address. This is in contrast to word-addressable architectures where the smallest addressable unit is an entire word. Consequently, consecutive bytes have consecutive addresses, and a 32-bit word spans four addressable byte locations.

Register Set

Register Set

NameRegister NumberUsage
zerox0Constant zero
rax1Return address
spx2Stack pointer
gpx3Global pointer
tpx4Thread pointer
t0-t2x5-7Temporary variables
s0x8Saved variable/frame pointer
s1x9Saved variable
a0-a1x10-11Function arguments/return values
a2-a7x12-17Function arguments
s2-s11x18-27Saved variables
t3-6x28-31Temporary variables
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Comments

In RISC-V, comments are started with a hash (#) symbol, e.g.:

# This is a comment
add a, b, c

Labels

Labels name instruction addresses in assembly code. They are written as identifiers followed by a colon (:) and are used as branch and jump targets.

loop:
	addi t0, t0, -1
	bne t0, zero, loop

Function Calling Convention

Caller:

  • passes arguments to callee
  • jumps to callee

Callee:

  • performs the function
  • returns result to caller
  • jumps to point of call
  • must not overwrite registers or memory needed by caller

Preserved values are the parts of machine state that must survive across a function call. The callee is responsible for saving and restoring them if it modifies them.

PreservedMeaning
s0, s1, s2-s11Callee-saved registers.
spThe stack pointer must be restored to its original value before returning.
raPreserved only if the callee itself performs another function call.
stack above spExisting stack data must not be overwritten.

Non-preserved values may be overwritten by the callee. If the caller still needs them after the call, it must save them first.

Non-preservedMeaning
t0-t6Caller-saved temporary registers.
a0-a7Argument and return-value registers.
stack below spSpace below the current stack pointer may be used for new stack frames.

Storing Register Values on the Stack

The following example saves one register on the stack, uses it as a temporary variable, and restores it before returning:

addi sp, sp, -4    # make space on stack for one word
sw   s0, 0(sp)     # save s0 on stack
addi s0, a0, 1     # use s0 as a temporary variable
add  a0, s0, zero  # put return value in a0
lw   s0, 0(sp)     # restore s0 from stack
addi sp, sp, 4     # deallocate stack space
jr   ra            # return to caller

Instructions

Definition

Instruction (RISC-V)

An instruction is a machine-level operation encoded as a binary word.

In the base RISC-V ISA, standard instructions are 32 bits wide. The compressed extension adds 16-bit compressed instructions.

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Compressed Instructions

Definition

Compressed Instruction (RISC-V)

A compressed instruction is a 16-bit RISC-V instruction encoding.

It is part of the compressed extension and represents a common operation in a shorter form than the standard 32-bit instruction. Compressed mnemonics are commonly prefixed with c..

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Floating Point Instructions

Definition

Floating-Point Instruction (RISC-V)

A floating-point instruction is a RISC-V instruction that operates on floating-point values in floating-point registers.

RISC-V offers three floating-point extensions:

  • RVF: single precision (32-bit)
    • 8 exponent bits
    • 23 fraction bits
  • RVD: double precision (64-bit)
    • 11 exponent bits
    • 52 fraction bits
  • RVQ: quad precision (128-bit)
    • 15 exponent bits
    • 112 fraction bits
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Privilege Mode

Definition

Privilege Mode (RISC-V)

A privilege mode is an execution level in RISC-V that controls which instructions, memory regions, and system resources a program may access.

RISC-V privilege modes are, from highest to lowest:

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Exceptions

Definition

Exception (RISC-V)

An exception is an event detected by the processor that transfers control to an exception handler.

In RISC-V, the handler address is stored in mtvec. The handler uses mcause to identify the cause of the exception, may save registers in mscratch, and can use mepc to resume execution after handling.

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Handling

When the processor detects an exception:

  • it jumps to the exception handler address in mtvec
  • the handler saves registers, often using mscratch
  • the handler reads mcause to determine the cause
  • the handler processes the exception
  • if execution should resume, the handler may increment mepc by 4
  • the handler restores registers and returns with mret

If the exception cannot be recovered from, the handler may abort the program instead of returning.

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Examples

Array Example

We want to translate the following C code to RISC-V:

int array[5];
array[0] = array[0] * 2;
array[1] = array[1] * 2;

Solution: First, we choose 0x123BF780 (arbitrary) as base address. Given that we can’t pass 32-bit immediate values, we have to do the trick from example 1:

# s0 = array base address
lui s0, 0x123B4     # 0x123B4 in the upper 20 bits of s0
addi s0, s0, 0x780  # s0 = 0x123Bf780

Next, we can load the value at index 0 to t1 (lw) and double it by shifting it by one bit (slli; i.e. doubling it) and writing the result back (sw):

lw t1, 0(s0)     # t1 = array[0]
slli t1, t1, 1   # t1 = t1 * 2
sw t1, 0(s0)     # array[0] = t1

Now we can repeat the previous step, but instead of using offset 0, we use offset 4 (as a C integer has 4 byte):

lw t1, 4(s0)     # t1 = array[1]
slli t1, t1, 1   # t1 = t1 * 2
sw t1, 4(s0)     # array[1] = t1

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