Lukas' Notes

191.003 Computer Systems

May 01, 20261 min read

  • Introduction:
    • Moore’s Law
    • Dennard Scaling
  • Building Blocks:
    • NMOS
    • PMOS
    • SR Latch
    • D Latch
    • D Flip-Flop
    • JK Flip-Flop
    • Counter
    • Shift Register
  • RISC-V
  • Microarchitecture:
    • Single-Cycle Processor
    • Multi-Cycle Processor
    • Parallelism
      • Amdahl’s Law
    • Pipelined Processor
      • Pipelined Hazard
        • Data Hazard
        • Control Hazard
          • Branch
          • Branch Instruction
          • Predicted Branch
          • Branch Misprediction Penalty
      • Pipeline Stage
        • Fetch Stage
        • Decode Stage
        • Execute Stage
        • Memory Access Stage
        • Writeback Stage
  • Memory Systems:
    • Memory
      • Memory System
      • Main Memory
      • RAM
        • SRAM
        • DRAM
        • DDRx Memory
        • High Bandwidth Memory
      • System Bus
      • Memory Controller
      • Memory Locality
        • Temporal Memory Locality
        • Spatial Memory Locality
    • Cache
      • Instruction Cache
      • Data Cache
      • Spatial Cache Locality
      • Cache Set
      • Cache Associativity
      • Direct-Mapped Cache
      • Set-Associative Cache
      • N-Way Set Associative Cache
      • Associative Cache
      • Fully Associative Cache
      • Cache Set Contention
      • Cache Miss
        • Compulsory Cache Miss
        • Conflict Cache Miss
        • Capacity Cache Miss
        • Cache Miss Penalty
      • Multi-level Cache
        • L1 Cache
        • L2 Cache
        • L3 Cache
      • Cache Write-Hit
      • Cache Write-Miss
      • Cache Replacement Policy
    • Memory Replacement Policy
      • Least Recently Used Memory Replacement Policy
      • First-In-First-Out Memory Replacement Policy

Graph View

Backlinks

  • TU Vienna

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