SR Latch

logic-circuits

Definition

SR Latch

An SR latch is composed of two cross-coupled NOR gates. The latch has two inputs, $S$ and $R$, and two outputs, $Q$ and $\bar{Q}$.

A NOR gate outputs false if one of the inputs is true. By walking through the possible cases, we can observe:

1. $R=1,S=0$: $N_1$ produces $false$ and $N_2$ produces $true$.
2. $R=0,S=1$: $N_2$ produces $false$ and $N_1$ produces $true$.
3. $R=1,S=1$: $N_1$ and $N_2$ produce $false$.
4. $R=0,S=0$: Since both inputs are $false$, we can’t directly determine the outputs. However, we can try to understand the behaviour of the latch.

Case 4a.) What if $Q=0$?

$$R=S=Q=0⟹\bar{Q}=1$$

Case 4b.) What if $Q=1$?

$$\begin{array}{r}R=S=0,Q=1⟹\bar{Q}=0\end{array}$$

We can use this two cases by introducing some known prior value, which we will call $Q_{prev}$, before we enter the third case. This prior value $Q_{prev}$ represents the state of the system. When $R=S=0$, $Q$ will remember this old value, $Q_{prev}$ and $\bar{Q}$ will be its complement ${\bar{Q}}_{prev}$. Thus, this circuit has memory.

Case	$S$	$R$	$Q$	$\bar{Q}$
4	$0$	$0$	$Q_{prev}$	${\bar{Q}}_{prev}$
1	$0$	$1$	0	$1$
2	$1$	$0$	1	$0$
3	$1$	$1$	0	$0$

We call $S$ set and $R$ reset signals.

To simplify the circuit symbolism, we can represent the latch as:

¹

Footnotes

1. Digital Design and Computer Architecture - RISC-V Edition ↩