Conflict Cache Miss

computer-architecture memory

Definition

Conflict Cache Miss

A conflict cache miss is a cache miss that occurs because multiple memory blocks map to the same cache set and cannot all stay in the cache at the same time.

Such misses arise from set contention, not because the cache is empty on first use and not because the total cache capacity is too small.

Example

Repeated conflict in a direct-mapped cache

Consider a loop that repeatedly loads the two words at addresses 0x4 and 0x24:

addi s0, zero, 5
addi s1, zero, 0
LOOP:
  beq  s0, zero, DONE
  lw   s2, 0x4(s1)
  lw   s4, 0x24(s1)
  addi s0, s0, -1
  j    LOOP
DONE:

In a direct-mapped cache, these two words may map to the same cache set. Then loading one word evicts the other.

So even though the loop repeatedly reuses the same two words, every access misses, because each load destroys the result of the previous one.

Over $5$ loop iterations, the program performs $10$ loads in total, and all $10$ are misses. Hence the miss rate is

$$\frac{10}{10}=100\%.$$