Definition
Pipeline Stage
A pipeline stage is one step of instruction processing in a pipelined processor.
Each instruction passes through a sequence of pipeline stages, and different instructions can be in different stages at the same time.
In a classic five-stage pipeline, the stages are fetch, decode, execute, memory access, and write-back.
Role
Why stages matter
Splitting instruction execution into stages makes temporal parallelism possible.
It also explains why hazards arise: different stages expose different information and make results available at different times.
Stages
Fetch
Definition
Link to originalFetch Stage
The fetch stage is the pipeline stage in which the next instruction is read from instruction memory.
Typically, the processor uses the current program counter to access instruction memory and fetch the instruction bits.
In a pipelined processor, this is usually the first stage of the pipeline.
Decode
Definition
Link to originalDecode Stage
The decode stage is the pipeline stage in which the fetched instruction is interpreted.
In this stage, the processor determines the instruction type, reads source registers, and derives the control signals needed for later stages.
Execute
Definition
Link to originalExecute Stage
The execute stage is the pipeline stage in which the main operation of an instruction is carried out.
For example, the ALU may perform an arithmetic or logical operation, compute an address, or evaluate a branch condition.
Memory access
Definition
Link to originalMemory Access Stage
The memory access stage is the pipeline stage in which the processor reads from or writes to data memory.
For a load instruction, this stage reads the requested value from memory. For a store instruction, it writes a value to memory.
Write-back
Definition
Link to originalWrite-Back Stage
The write-back stage is the pipeline stage in which a computed result is written into the destination register.
This may be an ALU result or a value loaded from memory.