RISC-V A-Extension

computer-architecture risc-v

Definition

RISC-V A-Extension

The RISC-V A-Extension is an ISA extension that provides atomic memory operations for synchronisation in shared-memory multicore systems. It specifies AMO (Atomic Memory Operation) instructions, LR/SC (Load-Reserved / Store-Conditional) pairs, and fence instructions for ordering.

Components

Atomic Memory Operations (AMO)

AMO instructions atomically read a value from memory, compute a new value, and write it back — all as a single indivisible bus transaction.

Examples:

• amoswap — atomic swap
• amoadd — atomic add
• amoxor — atomic XOR
• amoand, amoor, amomin, amomax, …

Load-Reserved / Store-Conditional (LR/SC)

LR/SC splits an atomic read-modify-write into two instructions:

• lr.w rd, (rs1) — loads a word from (rs1) into rd and registers a reservation on the address.
• sc.w rd, rs2, (rs1) — conditionally stores rs2 to (rs1) only if the reservation is still valid. rd receives zero on success, or a nonzero failure code.

The reservation is lost if any other hart accesses the same address. This allows building arbitrary atomic sequences without blocking the bus.

Fence

The fence instruction enforces memory ordering. It is parameterised by predecessor and successor sets:

fence pred, succ

where pred and succ are subsets of {r, w, i, o} (read, write, input, output). A common encoding is fence rw, w — no following write may become visible before all preceding reads and writes complete.

Instruction syntax

Instruction	Encoding	Semantics
amoswap.w.aq rd, rs2, (rs1)	AMO	Atomically: rd ← mem[rs1], mem[rs1] ← rs2
amoadd.w.aq rd, rs2, (rs1)	AMO	Atomically: rd ← mem[rs1], mem[rs1] ← mem[rs1] + rs2
lr.w rd, (rs1)	LR	rd ← mem[rs1], with reservation
sc.w rd, rs2, (rs1)	SC	If reservation holds: mem[rs1] ← rs2, rd ← 0; else rd ≠ 0
fence pred, succ	FENCE	Stall until all operations in pred complete before any in succ

Memory ordering suffixes

AMO and LR/SC instructions carry ordering suffixes:

• .aq (Acquire) — no following memory operation may be reordered before this instruction.
• .rl (Release) — no preceding memory operation may be reordered after this instruction.
• .aqrl — both acquire and release semantics, equivalent to sequentially consistent ordering.

These implement the release-acquire memory model at the instruction level.

Properties

Atomicity

AMO instructions are truly atomic — no other hart can observe an intermediate state of the memory location. LR/SC provides atomicity only when the store-conditional succeeds; on failure the sequence is retried.

Lock implementation

The combination of lr.w / sc.w enables a spinlock without holding the bus locked:

# a0 = address of lock variable
    li    a2, 1          # new value (locked)
.loop:
    lr.w  a1, (a0)       # load current lock value
    bnez  a1, .loop      # if already locked, spin
    sc.w  a3, a2, (a0)   # try to acquire
    bnez  a3, .loop      # if sc failed, retry

The unlock is a plain store: sw zero, (a0).

AMO vs LR/SC

AMO instructions are simpler and guarantee forward progress. LR/SC is more flexible — it can implement any read-modify-write sequence — but requires a retry loop since sc.w may spuriously fail.

Reservation granularity

The reservation is typically per cache block. Any store to the same block by another hart, or certain cache coherence events, clears the reservation.