Definition
Cache Coherence
Cache coherency is the property of a multi-core memory system that ensures every read to a memory location returns the most recent write to that location, regardless of which core performed the write.
The Problem
In a multi-core processor with private caches, each core holds its own copy of a cache block. When one core writes to a block, copies in other cores’ caches become stale — they still hold the old value.
Without a coherence mechanism, a later read by another core may return the stale cached copy instead of the updated value in memory or in the writing core’s cache.
Coherence Controller
Each cache is paired with a coherence controller that:
- Snoops bus transactions — checks the cache tag array to see if it holds the block involved in the transaction.
- Tracks state per cache block via a finite state machine implementing the coherence protocol.
- Responds to snooped requests — supplies data to other caches or invalidates its copy as required.
- Queues outgoing data in a write-back buffer.
The coherence controllers communicate over the shared interconnect (bus).
Coherence Protocols
Coherence protocols define the state machine per cache block and the rules for snooped bus transactions. Common protocols:
| Protocol | Caches | States |
|---|---|---|
| Write-through | Write-through | V (Valid) |
| MSI | Write-back | M, S, I |
| MESI | Write-back | M, E, S, I |
| MOESI | Write-back | M, O, E, S, I |
A write-through protocol is the simplest: every write goes to memory, so other caches always see the update. Write-back protocols are more complex but reduce bus traffic.