Control and Status Register (RISC-V)

risc-v

Definition

Control and Status Register (RISC-V)

A control and status register is a special register used to handle exceptions and other privileged processor state.

Control and status registers are grouped by privilege mode. For example, machine mode uses mtvec, mcause, mepc, and mscratch.

Machine mode

Machine-mode control and status registers include:

• mtvec
• mcause
• mepc
• mscratch

Supervisor mode

Supervisor-mode control and status registers include:

• stvec
• scause
• sepc
• sscratch

Other privilege modes have their own control and status registers as well.