Definition
Hardware State Machine
A hardware state machine is a finite-state description of a sequential circuit.
It specifies:
- the finite set of control states;
- the transition condition for moving from one state to the next;
- the outputs or control signals produced in each state.
In a synchronous circuit, the machine usually changes state on a positive clock edge.
In processor design, a hardware state machine is often used to describe the control unit at a high level. Each state corresponds to one step of instruction processing, such as fetch, decode, memory access, or write-back.
Example: in a multi-cycle processor, one state may fetch the instruction, the next may decode it, and a later state may write a result back to the register file.
Reading the diagram
State-machine view of a circuit
In such a diagram:
- a node represents one control state;
- the text inside the node gives the control signals asserted in that state;
- an edge represents a possible transition to the next state;
- the label on an edge gives the condition for taking that transition;
- the reset edge marks the initial state.
So the diagram does not show all wires of the circuit. Instead, it shows the control flow of the circuit at a higher level.
Example
Multi-cycle processor control
In a multi-cycle processor, the control unit is naturally described by a hardware state machine.
For example, one state may perform instruction fetch, another may decode the instruction, and later states may handle memory access or register write-back. The next state depends on the current state together with information such as the opcode.
This is why a multi-cycle control diagram often looks like a state diagram rather than a datapath: it describes which control signals are active in each cycle, and how the processor moves from one control step to the next.