Definition
Commit Stage
The commit stage (also retire stage) is the pipeline stage in which a completed instruction’s result is written to architectural register state.
Results are committed in program order, regardless of the order in which instructions executed. This guarantees precise exceptions: when an instruction raises an exception, all earlier instructions have committed and no later instruction has altered architectural state.
Reorder Buffer
In-order commit is typically implemented with a reorder buffer (ROB). The ROB holds completed results in program order. The commit stage retires instructions from the head of the ROB.
An instruction at the ROB head commits only when it has completed execution. If the head is not yet complete — because a long-latency instruction is still executing — all later instructions, even those that have already finished, wait behind it.
In a superscalar processor, multiple instructions may commit per cycle, increasing commit bandwidth beyond one instruction per cycle.