Definition
Thread-Level Parallelism
Exploitation
TLP is exploited by two hardware approaches:
- Hardware multi-threading — multiple threads share the functional units of a single core. The processor switches rapidly between threads to hide pipeline and memory latencies, improving single-core throughput (IPC).
- Multi-core processors — each core executes a separate thread independently. This is the more general method, and modern platforms often combine multi-core with per-core multi-threading.
TLP vs ILP
| ILP | TLP | |
|---|---|---|
| Source | Within one thread | Across threads |
| Found by | Compiler + hardware | Programmer / OS |
| Hardware | Superscalar, OoO, VLIW | MT, multi-core |
| Improves | Single-thread throughput | Multi-thread throughput |
TLP and ILP are complementary. A simultaneous multi-threaded (SMT) core exploits both at once.