Definition
Out-of-Order Pipelined Processor
An out-of-order pipelined processor is a pipelined processor in which instructions can execute out of program order, as long as data dependencies are respected.
Results are committed in program order, so the architectural state always reflects sequential execution.
In-order commit
Although instructions execute out of order, results are written to architectural state in program order. This guarantees precise exceptions: when an instruction raises an exception, all earlier instructions have completed and no later instruction has modified architectural state.
In-order commit is typically implemented with a reorder buffer that holds completed results until all earlier instructions have also committed.
Dynamic scheduling
Instructions wait in reservation stations until their operands are available. When an operand is produced, it is broadcast on a common data bus, and any waiting instruction that needs it can wake up and issue.
This allows independent instructions to bypass a stalled instruction and execute ahead, hiding pipeline stall latency.
False dependency elimination
An out-of-order pipelined processor uses register renaming to eliminate write-after-read and write-after-write hazards. Each write to an architectural register gets a fresh physical register, so independent writes to the same register do not collide.
Read-after-write hazards remain, because they represent true dataflow.