Definition
Memory Ordering Violation
A memory ordering violation occurs when a younger load instruction executes before an older store instruction to the same memory address, and the load reads a stale value from the cache instead of the value produced by the store.
This can happen in an out-of-order pipelined processor when the store address is not yet known at the time the load issues.
Detection
The load-store unit detects memory ordering violations by tracking in-flight loads and stores. When a store address is resolved, the store checks the load queue for younger loads that have already executed and read the same address.
If a younger load read a matching address before the store committed, the load and all dependent instructions must be squashed and replayed.
Example
Store followed by load to the same address
SW t1, 0(a0) ; store to address X LW t2, 0(a1) ; load from address X (a1 == a0)If the store address is computed late and the load issues early, the load reads the old value from cache. When the store address resolves to the same address, the violation is detected. The load and its dependents are replayed, this time receiving the forwarded value from the store buffer.