Lukas' Notes

computer-architecture

Definition

Store Buffer

A store buffer is a queue of pending store instructions that have been issued by the processor but not yet written to the data cache.

Once a store enters the buffer, the pipeline can proceed without waiting for the cache write to complete. The store buffer decouples store execution from store commit.

Store-to-load forwarding

A later load instruction that reads the same memory address as a pending store must receive the buffered value, not the stale value still in the cache. The store buffer checks each load address against its entries and forwards the data from the youngest matching store.

This is done in the load-store unit during the memory access stage.

Retirement and commit

In an out-of-order pipelined processor, stores remain in the store buffer until retirement. A store only becomes visible to the memory system after all earlier instructions have committed, preserving precise exceptions.

In a static in-order pipeline, stores may drain from the buffer to cache as soon as the cache port is free, since the pipeline already enforces program order.