Definition
Static In-order Scheduling with Load-Store Optimization
Static in-order scheduling with load-store optimization extends static in-order scheduling with pipelined functional units by allowing multiple non-blocking loads and buffered stores to proceed without occupying the execute stage.
A store posted to the store buffer does not count as an instruction in the execute stage. A load can issue as long as the load queue is not full. The execute stage stalls only when the store buffer or load queue reaches capacity.
Store buffer decoupling
Once a store has computed its address, it enters the store buffer and releases the execute stage. The store buffer drains to the data cache independently, while the pipeline continues with younger instructions.
This hides store latency: an instruction that follows a store can enter the execute stage while the store is still buffered.
Load queue capacity
Multiple non-blocking loads can occupy the memory pipeline simultaneously, up to the depth of the load queue. An independent load can issue past a stalled load, as long as a load queue entry is free.
When the load queue is full, the execute stage stalls and later instructions back-propagate.
Example
Store buffer hides store latency