Non-blocking Load Instruction

computer-architecture

Definition

Non-blocking Load Instruction

A non-blocking load instruction is a load instruction that does not stall the pipeline while waiting for data from the memory system.

Independent instructions that follow the load can issue and execute while the load is in flight. Only instructions that consume the loaded value must wait.

Behaviour

A non-blocking load requires the processor to track outstanding loads, typically with a load queue or miss-status holding register. When the data returns, dependent instructions are woken up.

This is only possible in an out-of-order pipelined processor. A static in-order pipeline cannot issue instructions past a stalled load, so every load is a blocking load.

Examples

Two loads, one miss

Consider a non-blocking load-store unit that returns results in program order.

LW  t1, 0(a0)    ; cache miss — 4 memory cycles
LW  t2, 0(a1)    ; cache hit, but LSU returns in-order
ADD t1, t1, t2   ; depends on both loads

Even though the second load hits in the cache, its result cannot commit before the first load finishes. The ADD stalls until both values are available.