Write-after-Read Dependency

computer-architecture

Definition

Write-after-Read Dependency

A write-after-read (WAR) dependency (also anti-dependency) is a data hazard in which an instruction $I_2$ writes to a register that a preceding instruction $I_1$ reads.

$$I_1:\text{read}(r)I_2:\text{write}(r)\text{with }{I}_1{\prec }_{\text{prog}}{I}_2$$

$I_2$ must not overtake $I_1$ in the pipeline. If $I_2$ writes $r$ before $I_1$ reads it, $I_1$ reads the wrong value.

This is a false dependency: $I_2$ does not depend on any value produced by $I_1$. The conflict arises only because both instructions share the same register name. Register renaming eliminates WAR hazards by assigning $I_2$ a fresh physical register.

Examples

Vector Addition Loop

Consider a loop body that computes $\mathbf{c}=\mathbf{a}+\mathbf{b}$:

LW  t1, 0(a0)     # reads a0
LW  t2, 0(a1)     # reads a1
ADD t1, t1, t2    # t1 = a[i] + b[i]
SW  t1, 0(a2)     # c[i] = t1, reads a2
ADDI a0, a0, 4    # writes a0
ADDI a1, a1, 4    # writes a1
ADDI a2, a2, 4    # writes a2

Three WAR dependencies exist:

Read	Write	Register
LW t1, 0(a0)	ADDI a0, a0, 4	a0
LW t2, 0(a1)	ADDI a1, a1, 4	a1
SW t1, 0(a2)	ADDI a2, a2, 4	a2

If any ADDI overtakes its preceding read, the base address is corrupted and the subsequent memory access uses the wrong pointer.