Read-after-Write Dependency

computer-architecture

Definition

Read-after-Write Dependency

A read-after-write (RAW) dependency (also true dependency) is a data hazard in which an instruction $I_2$ reads a register that a preceding instruction $I_1$ writes.

$$I_1:\text{write}(r)I_2:\text{read}(r)\text{with }{I}_1{\prec }_{\text{prog}}{I}_2$$

If $I_2$ enters the execute stage before $I_1$ has completed write-back, $I_2$ reads a stale value. This is a true dependency: $I_2$ genuinely requires the value that $I_1$ produces.

Unlike WAR and WAW dependencies, a RAW dependency cannot be eliminated by register renaming — the data flow between $I_1$ and $I_2$ is real. In out-of-order execution, $I_2$ must wait in the issue buffer until $I_1$ produces its result.

Examples

XOR / ADD Chain

XOR a1, a2, a4    # writes a1
ADD a3, a1, t1    # reads a1

ADD requires the result of XOR. If the pipeline proceeds without a stall or forwarding, ADD reads the old value of a1.

Vector Addition Loop

Consider a loop body that computes $\mathbf{c}=\mathbf{a}+\mathbf{b}$:

LW  t1, 0(a0)     # writes t1
LW  t2, 0(a1)     # writes t2
ADD t1, t1, t2    # reads t1, t2; writes t1
SW  t1, 0(a2)     # reads t1
ADDI a0, a0, 4
ADDI a1, a1, 4
ADDI a2, a2, 4
ADDI t0, t0, 1    # writes t0
BLTU t0, t3, vec_add_for  # reads t0, t3

Four RAW dependencies exist:

Write	Read	Register
LW t1, 0(a0)	ADD t1, t1, t2	t1
LW t2, 0(a1)	ADD t1, t1, t2	t2
ADD t1, t1, t2	SW t1, 0(a2)	t1
ADDI t0, t0, 1	BLTU t0, t3, vec_add_for	t0

Multi-Cycle Functional Unit

When a load is followed by an arithmetic instruction that uses the loaded value:

LW   t1, 0(a3)     # memory access takes multiple cycles
ADDI t1, t1, 4     # needs t1

The load completes its memory access in a later cycle than a single-cycle ALU operation. ADDI must stall in the decode stage until the load writes back, unless forwarding from the memory stage is available.

With a multi-cycle divider (e.g. 64 cycles in the CVA6 processor), a dependent instruction may be blocked in the issue buffer for dozens of cycles.