Definition
Issue Stage
The issue stage is the pipeline stage in which a decoded and renamed instruction is dispatched to a functional unit for execution.
An instruction can issue only when:
- all its source operands are ready (no outstanding RAW dependencies),
- the required functional unit is free.
Instructions that cannot issue immediately wait in the issue buffer or a reservation station.
Issue Buffer
The issue buffer holds instructions that have passed decode and rename but are not yet ready to execute. Each entry tracks the operands and marks them as ready when they are produced.
This is the point where out-of-order execution becomes visible: an instruction stalled in the issue buffer does not block later independent instructions from issuing. The issue stage picks a ready instruction each cycle, regardless of program order.
In a superscalar processor, multiple instructions may issue per cycle, subject to issue bandwidth and functional unit availability.
Wakeup
When an instruction completes execution, its result tag is broadcast. Waiting instructions that need that result match the tag, mark the operand as ready, and may then issue in a later cycle.