Definition
Instruction Cache Miss
An instruction cache miss is a cache miss in the instruction cache. It occurs during the fetch stage when the next instruction to fetch is not present in the I-cache.
The required cache block must be fetched from a lower level of the memory hierarchy, such as main memory, before the fetch stage can proceed.
Pipeline stall
An instruction cache miss stalls the fetch stage. No new instructions enter the pipeline until the missing block arrives, so the stall back-propagates as pipeline stages drain.
In a static in-order pipeline, every cycle of the miss penalty is a cycle in which no useful work enters the pipeline. In an out-of-order design, independent instructions already in flight can still execute, but the pipeline eventually drains if the miss is long enough.
Instruction prefetching reduces the instruction cache miss rate by fetching lines before the fetch stage demands them.